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VHDL code for quadrature encoder receiver module

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Original document: Quadrature Encoder Receiver Module : An Implementation on FPGA (.pdf) In the original document cited above, we discussed some designs of quadrature encoder receiver module where Verilog code listings were included. This supplementary article provides the same implementations using VHDL. The development flows remain the same for both design A and B, so we basically list the codes and show simulation results here without repeating the design details. Design A For Design A, the receiver module generates pulses at output pin U (up) or D (down), corresponding to whether A leads B, or A lags B, respectively (*). We showed the design process using STG (State Transition Graph) that yielded the results in equation (1) – (4) . The VHDL code for this implementation is in Listing 1 with simulation result shown in Figure 1. (The synthesis and behavioral simulation was performed using Xilinx Webpack 13.4 and Isim simulation, which could be downloaded from Xilinx website . (...
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An Introduction to Finite State Machine Design

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Roughly speaking, a synchronous Finite State Machine (FSM) refers to a digital circuit/system that has memory, and is driven by a clock signal to change from one state to another depending on the applied input and its previous state. This classification covers from the simplest circuit consisting of only one D flip-flop, to a high-performance computer system. One might refer to FSM as a sequential circuit, in contrast to a combinational circuit that is memoryless. With latest electronics/computer technology, an FSM of low to medium complexity can be designed and implemented rather easily using CPLD/FPGA and software tools. The main advantages of this approach are flexibility, compactness, and ease of maintenance. Hardwiring TTL/CMOS logic gate and DFF ICs together on a PCB is now considered outdated. Previously on this website, we discussed some design and implementation of quadrature encoder interface circuits (see, for example, VHDL code for quadrature encoder receiver module an...
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A Note on Output Compare (PWM) Module of PIC24E

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A while ago on www.controlsystemslab.com (no longer maintained), we present an article on DC motor open-loop speed control , using a simple voltage command from ADC to drive the H-bridge driver. The PWM output is generated from output compare module of the dsPIC30F2010. That 16-bit digital signal processor is now quite dated. The reader would want to implement the scheme on a newer microcontroller. At the time of this writing, PIC24EP (and dsPIC33E) series from Microchip is the latest product in the 16-bit range that could run at 70 MIPS performance. For those who want to port the code to PIC24EP, unfortunately, you have to modify the ADC and PWM routines. In this article we focus on the latter.
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